Invention Grant
- Patent Title: Wire lineend to via overlap optimization
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Application No.: US15805178Application Date: 2017-11-07
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Publication No.: US10394992B2Publication Date: 2019-08-27
- Inventor: Rasit O. Topaloglu
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Monchai Chuaychoo
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G03F1/36

Abstract:
An approach for shifting a cut associated with a lineend of an interconnect in a manufacturing system. The approach selects one or more polygons associated with the lineend and determines whether a first cut is spanning the one or more polygons. The approach responds to the first cut does span, determines a presence of a first via on a first interconnect and determines a first distance of the first via to the first cut. The approach determines whether the first distance is greater than a first threshold and responds to the first distance is greater and determines whether the first distance is greater and determines a second distance of the first cut to a second cut. The approach determines whether the second distance is greater than a second threshold and responds to the second distance is greater and generates a shift associated with the first cut and outputs the shift.
Public/Granted literature
- US20190138681A1 WIRE LINEEND TO VIA OVERLAP OPTIMIZATION Public/Granted day:2019-05-09
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