Invention Grant
- Patent Title: Multilayer pillar for reduced stress interconnect and method of making same
-
Application No.: US15405431Application Date: 2017-01-13
-
Publication No.: US10396051B2Publication Date: 2019-08-27
- Inventor: Virendra R. Jadhav , Krystyna W. Semkow , Kamalesh K. Srivastava , Brian R. Sundlof
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran Cole & Calderon P.C.
- Agent Jennifer Anda; Andrew M. Calderon
- Main IPC: H01L23/00
- IPC: H01L23/00
Abstract:
A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
Public/Granted literature
- US20170133338A1 MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME Public/Granted day:2017-05-11
Information query
IPC分类:
