Invention Grant
- Patent Title: Semiconductor device and method of manufacturing semiconductor device
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Application No.: US15889244Application Date: 2018-02-06
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Publication No.: US10396153B2Publication Date: 2019-08-27
- Inventor: Takehiro Ueda
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Mattingly & Malur, PC
- Priority: JP2017-070444 20170331
- Main IPC: H01L29/15
- IPC: H01L29/15 ; H01L29/06 ; H01L29/205 ; H01L21/265 ; H01L29/778 ; H01L29/66 ; H01L21/761 ; H01L29/40 ; H01L29/423 ; H01L29/20

Abstract:
A high-electron-mobility transistor has a buffer layer, a channel layer, a barrier layer, a mesa-shaped cap layer, a source electrode formed on one side of the cap layer, a drain electrode formed on the other side, and a gate electrode formed over the cap layer via a gate insulating film. The semiconductor device has an element isolation region defining an active region in which the semiconductor device is provided. The gate electrode extends from over the active region to the over the element isolation region. In plan view, the active region has a projection part projected to the direction of the element isolation region in a region overlapped with the gate electrode. By providing the active region with a projection part, the channel length of a parasitic transistor can be increased, and turn-on of the parasitic transistor can be suppressed.
Public/Granted literature
- US20180286948A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2018-10-04
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