Described is an apparatus which comprises: a plurality of transmitter circuits on a first die; a plurality of receiver circuits on a second die; a plurality of data transmission lines communicatively coupling the first die to the second die for the plurality of transmitter circuits to transmit data bits in parallel to the plurality of receiver circuits; a termination circuit comprising a shared capacitor and a plurality of resistors, each corresponding to one of the plurality of conductive lines and each coupled to the shared capacitor; and a parallel coding block to code data transmitted by the plurality of transmitter circuits via the plurality of data transmission lines according to a direct current (DC) balanced code.