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    Approximate data bus inversion technique for latency sensitive applications
    1.
    发明授权
    Approximate data bus inversion technique for latency sensitive applications 有权

    公开(公告)号：US12117960B2

    公开(公告)日：2024-10-15

    申请号：US17029288

    申请日：2020-09-23

    Applicant: Intel Corporation

    Inventor： Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald S. Pasdast ,  Zuoguo Wu

    IPC: G06F13/42 ,  G06F13/40

    CPC classification number: G06F13/4291 ,  G06F13/4068 ,  G06F13/423

    Abstract: Systems, methods, and apparatuses associated with an approximate majority based data bus inversion technique are disclosed. A method comprises obtaining, at a first device connected by a plurality of lanes to a second device, original data comprising first bits and second bits, where the first bits are to be transmitted in a new clock cycle via first lanes of the plurality of lanes, and the second bits are to be transmitted in the new clock cycle via second lanes of the plurality of lanes. The method further includes determining whether a first criterion associated with the first bits is met, determining whether a second criterion associated with the second bits is met, and transmitting an inverted version of the original data via the plurality of lanes based, at least in part, on determining that the first criterion and the second criterion are met.

    DIE-TO-DIE INTERCONNECT
    3.
    发明申请
    DIE-TO-DIE INTERCONNECT 有权

    公开(公告)号：US20220342840A1

    公开(公告)日：2022-10-27

    申请号：US17852865

    申请日：2022-06-29

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Swadesh Choudhary ,  Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu

    IPC: G06F13/42

    Abstract: A port is to couple to another die over a die-to-die (D2D) link and includes physical layer (PHY) circuitry including a first number of sideband lanes to carry data for use in training and management of the D2D link, and a second number of mainband lanes to implement a main data path of the D2D link. The mainband lanes include a forwarded clock lane, a valid lane, and a plurality of data lanes. A logical PHY coordinates functions of the sideband lanes and the mainband lanes.

    Valid lane training
    6.
    发明授权
    Valid lane training 有权

    公开(公告)号：US10461805B2

    公开(公告)日：2019-10-29

    申请号：US15761408

    申请日：2015-09-26

    Applicant: Intel Corporation

    Inventor： Venkatraman Iyer ,  Lip Khoon Teh ,  Mahesh Wagh ,  Zuoguo Wu ,  Azydee Hamid ,  Gerald S. Pasdast

    IPC: H04B3/40 ,  G06F13/20 ,  H04L25/03

    Abstract: One or more link training signals are received, including instances of a link training pattern, on a plurality of lanes of a physical link that includes at least one valid lane and a plurality of data lanes. The plurality of lanes are trained together using the link training signals to synchronize sampling of the valid lane with sampling of the plurality of data lanes. An active link state is entered and a valid signal received on the valid lane during the active link state. The valid signal includes a signal held at a value for a defined first duration and indicates that data is to be received on the plurality of data lanes in a second defined duration subsequent to the first duration. The data is to be received, during the active link state, on the plurality of data lanes during the second defined duration.

    High speed short reach input/output (I/O)
    7.
    发明授权
    High speed short reach input/output (I/O) 有权

    公开(公告)号：US10396840B2

    公开(公告)日：2019-08-27

    申请号：US14142595

    申请日：2013-12-27

    Applicant: INTEL CORPORATION

    Inventor： Zuoguo Wu

    IPC: H04B1/38 ,  H04L25/02 ,  H04L25/49

    Abstract: Described is an apparatus which comprises: a plurality of transmitter circuits on a first die; a plurality of receiver circuits on a second die; a plurality of data transmission lines communicatively coupling the first die to the second die for the plurality of transmitter circuits to transmit data bits in parallel to the plurality of receiver circuits; a termination circuit comprising a shared capacitor and a plurality of resistors, each corresponding to one of the plurality of conductive lines and each coupled to the shared capacitor; and a parallel coding block to code data transmitted by the plurality of transmitter circuits via the plurality of data transmission lines according to a direct current (DC) balanced code.

    APPARATUS AND METHOD FOR CLASSIFYING AND LOCATING ELECTRICAL FAULTS IN CIRCUITRY
    8.
    发明申请
    APPARATUS AND METHOD FOR CLASSIFYING AND LOCATING ELECTRICAL FAULTS IN CIRCUITRY 审中-公开

    公开(公告)号：US20180284185A1

    公开(公告)日：2018-10-04

    申请号：US15474674

    申请日：2017-03-30

    Applicant: Intel Corporation

    Inventor： Mayue Xie ,  Zhiguo Qian ,  Jong-Ru Guo ,  Zhichao Zhang ,  Zuoguo Wu

    IPC: G01R31/28

    Abstract: A die with a transmission circuit, a reception circuit, and a comparison circuit can be provided. The transmission circuit can be configured to transmit a first signal through a first channel at a first transmission rate and a first transmission amplitude. The reception circuit can be in communication with the transmission circuit through the first channel. The reception circuit can receive a second signal at a first reception rate and at a first reception amplitude. The comparison circuit can be in communication with the transmission circuit and the reception circuit. The comparison circuit can be configured to: determine a first rate error value, determine a first amplitude error value, compare the first rate error value with a rate threshold to determine a first rate error occurrence, and compare the first amplitude error value with an amplitude threshold to determine a first amplitude error occurrence.

    PSEUDORANDOM BIT SEQUENCES IN AN INTERCONNECT
    9.
    发明申请
    PSEUDORANDOM BIT SEQUENCES IN AN INTERCONNECT 审中-公开
    互连中的PSEUDORANDOM位比特序列

    公开(公告)号：US20160285624A1

    公开(公告)日：2016-09-29

    申请号：US14669743

    申请日：2015-03-26

    Applicant: Intel Corporation

    Inventor： Mahesh Wagh ,  Zuoguo Wu ,  Venkatraman Iyer

    IPC: H04L9/06

    CPC classification number: H04B3/46 ,  H04B3/32 ,  H04B3/487

    Abstract: In an example, a linear feedback shift register (LFSR) provides pseudorandom bit sequences (PRBSs) to an interconnect for training, testing, and scrambling purposes. The interconnect may include a state machine, with states including LOOPBACK, CENTERING, RECENTERING, and ACTIVE states, among others. The interconnect is permitted to move from “CENTERING” to “LOOPBACK” via a sideband signal. In LOOPBACK, CENTERING, and RECENTERING, PRBSs are used for training and testing purposes to electrically characterize and test the interconnect, and to locate a midpoint for a reference voltage Vref. A unique, noncorrelated PRBS is provided to each lane, calculated using one common output bit.

    Abstract translation: 在一个示例中，线性反馈移位寄存器（LFSR）向用于训练，测试和加扰目的的互连提供伪随机比特序列（PRBS）。 互连可以包括状态机，其中包括LOOPBACK，CENTERING，RECENTERING和ACTIVE状态等状态。 互连允许通过边带信号从“CENTERING”移动到“LOOPBACK”。 在LOOPBACK，CENTERING和RECENTERING中，PRBS用于训练和测试目的，用于对互连进行电性能和测试，并定位参考电压Vref的中点。 使用一个公共输出位计算每个通道提供一个独特的，不相关的PRBS。

    HIGH PERFORMANCE OPTICAL REPEATER
    10.
    发明申请
    HIGH PERFORMANCE OPTICAL REPEATER 有权
    高性能光学重复器

    公开(公告)号：US20160182154A1

    公开(公告)日：2016-06-23

    申请号：US14577979

    申请日：2014-12-19

    Applicant: Intel Corporation

    Inventor： Jing Fang ,  Zuoguo Wu ,  Venkatraman Iyer

    IPC: H04B10/29 ,  H04B10/2575

    CPC classification number: H04B10/29 ,  H04B10/2575

    Abstract: An optical element is to be coupled to a second device by the second electrical link. The particular optical element is further to receive a first signal from the second device over a first inbound lane of the second electrical link, receive a second signal from the second device over a second inbound lane of the second electrical link, and multiplex the first and second signals on a particular optical link to send the first and second signals to the first device.

    Abstract translation: 光学元件将通过第二电连接件耦合到第二装置。 所述特定光学元件还用于通过所述第二电连接的第一入口通道从所述第二设备接收第一信号，在所述第二电连接的第二入站通道上从所述第二设备接收第二信号，并且将所述第一和第 在特定光链路上的第二信号以将第一和第二信号发送到第一设备。

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