Invention Grant
- Patent Title: Memory access for busy memory by receiving data from cache during said busy period and verifying said data utilizing cache hit bit or cache miss bit
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Application No.: US15032329Application Date: 2013-10-31
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Publication No.: US10402324B2Publication Date: 2019-09-03
- Inventor: Kevin T. Lim , Sheng Li , Parthasarathy Ranganathan , William C. Hallowell
- Applicant: Hewlett Packard Enterprise Development LP
- Applicant Address: US TX Houston
- Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Current Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Current Assignee Address: US TX Houston
- Agency: Hewlett Packard Enterprise Patent Department
- International Application: PCT/US2013/067756 WO 20131031
- International Announcement: WO2015/065426 WO 20150507
- Main IPC: G06F12/0802
- IPC: G06F12/0802 ; G06F13/38
Abstract:
According to an example, a processor generates a memory access request and sends the memory access request to a memory module. The processor receives data from the memory module in response to the memory access request when a memory device in the memory module for the memory access request is busy and unable to execute the memory access request.
Public/Granted literature
- US20160275014A1 MEMORY ACCESS FOR BUSY MEMORY Public/Granted day:2016-09-22
Information query
IPC分类:
