Methods according to the disclosure include: predicting process-sensitive geometries (PSGs) in a proposed IC layout based on violations of a set of processing constraints for the proposed IC layout, the set of processing constraints being calculated with a predictive model based on a training data repository having a plurality of optical rule check (ORC) simulations for different IC layouts; identifying actual PSGs in a circuit manufactured using the proposed IC layout; determining whether the predicted PSGs correspond to the actual PSGs in the manufactured circuit as being correct; in response to the predicting being incorrect: adjusting the predictive model based on the actual PSGs, wherein the adjusting includes submitting additional ORC data to the training data repository; and flagging the proposed IC layout as incorrectly predicted; and in response to the predicting being correct, flagging the proposed IC layout as correctly predicted.