Invention Grant
- Patent Title: Chip package assembly with enhanced interconnects and method for fabricating the same
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Application No.: US15798748Application Date: 2017-10-31
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Publication No.: US10403591B2Publication Date: 2019-09-03
- Inventor: Jaspreet Singh Gandhi
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agent Keith Taboada
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/00 ; H01L23/00 ; H01L23/498 ; H01L21/48

Abstract:
An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a first substrate containing first circuitry, a first contact pad, a first pillar, a first pillar protection layer, a second substrate containing second circuitry, and a solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second substrate. The first contact pad is disposed on the first substrate and coupled to the first circuitry. The first pillar electrically disposed over the first contact pad. The first pillar protection layer is hydrophobic to solder and is disposed on a side surface of the first pillar.
Public/Granted literature
- US20190131265A1 CHIP PACKAGE ASSEMBLY WITH ENHANCED INTERCONNECTS AND METHOD FOR FABRICATING THE SAME Public/Granted day:2019-05-02
Information query
IPC分类: