Invention Grant
- Patent Title: Methods of fabricating semiconductor devices
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Application No.: US15877563Application Date: 2018-01-23
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Publication No.: US10411129B2Publication Date: 2019-09-10
- Inventor: Shigenobu Maeda , Tae-Yong Kwon , Sang-Su Kim , Jae-Hoo Park
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Agency: Muir Patent Law, PLLC
- Priority: KR10-2014-0101756 20140807
- Main IPC: H01L31/072
- IPC: H01L31/072 ; H01L31/109 ; H01L29/78 ; H01L21/8234 ; H01L27/088 ; H01L29/66 ; H01L29/165 ; H01L21/02 ; H01L21/8238 ; H01L27/092 ; H01L29/08 ; H01L29/16 ; H01L29/161

Abstract:
Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.
Public/Granted literature
- US20180151736A1 Methods of Fabricating Semiconductor Devices Public/Granted day:2018-05-31
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