Invention Grant
- Patent Title: System and method for reducing output harmonics
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Application No.: US15875583Application Date: 2018-01-19
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Publication No.: US10411583B2Publication Date: 2019-09-10
- Inventor: Sriharsha Vasadi , Mustafa H. Koroglu , Sherry X. Wu
- Applicant: Silicon Laboratories Inc.
- Applicant Address: US TX Austin
- Assignee: SILICON LABORATORIES INC.
- Current Assignee: SILICON LABORATORIES INC.
- Current Assignee Address: US TX Austin
- Agency: Polansky & Associates, P.L.L.C.
- Agent Paul J. Polansky
- Main IPC: H02M1/10
- IPC: H02M1/10 ; H02M1/12 ; H02J3/01 ; H03F3/21 ; H02M1/00

Abstract:
In one form, a power amplifier system includes first and second amplification path, and a combination element. The first amplification path has an input for receiving a drive signal, and an output. The second amplification path has an input coupled to the input of the first amplification path, and an output. The second amplification path has a delay element that inserts a signal path delay with respect to the first amplification path, wherein the delay element has a delay corresponding to a harmonic that is desired to be reduced. The combination element is coupled to the output of the first amplification path and an output of the second amplification path, and provides an output signal as a sum of outputs of the first amplification path and the second amplification path.
Public/Granted literature
- US20190229608A1 SYSTEM AND METHOD FOR REDUCING OUTPUT HARMONICS Public/Granted day:2019-07-25
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