An array substrate includes a substrate and a gate electrode, a gate insulating layer, a channel layer, an insulating layer, and a passivation layer sequentially formed on the surface of the substrate. An oxide semiconductor layer that forms a channel layer and a plurality of first IPS electrodes that are spaced from the oxide semiconductor layer are provided on the gate insulating layer. The insulating layer covers the oxide semiconductor layer and the plurality of first IPS electrodes. The passivation layer covers the channel layer and is formed with trenches. The trenches are located on a side of each of the first IPS electrode and extending to the gate insulation layer. Second IPS electrodes are formed on the passivation layer and corresponding to the first IPS electrodes and are connected to the first IPS electrodes.