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公开(公告)号：US11411101B2
公开(公告)日：2022-08-09
申请号：US16609440
申请日：2019-06-18
发明人： Xianwang Wei
摘要： A TFT substrate and a manufacturing method thereof are provided. In the manufacturing method, a metal oxide semiconductor layer is irradiated with UV light by using a gate as a shielding layer, such that a portion of the metal oxide semiconductor layer irradiated by the UV light is conductorized to form a source, a drain, and a pixel electrode, and a portion of the metal oxide semiconductor layer shielded by the gate still retains semiconductor properties to form a semiconductor channel. The invention achieves the alignment of the source and the drain with the gate by processes of self-alignment of the gate and conductorization of the metal oxide semiconductor layer, and can effectively control an overlapping region of the source and drain and the gate. Thereby, the parasitic capacitance is reduced, and the display quality is improved. Also, the manufacturing method is simple, and the production efficiency is improved.
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2.发明申请公开(公告)号：US20190018293A1
公开(公告)日：2019-01-17
申请号：US16134934
申请日：2018-09-18
发明人： Xianwang Wei , Yang Liu
IPC分类号： G02F1/1343 , G02F1/1335 , G02F1/1333 , H01L27/12
CPC分类号： G02F1/134363 , G02F1/133345 , G02F1/13439 , G02F2201/121 , H01L27/1225 , H01L27/124 , H01L27/1259 , H01L27/127
摘要： An array substrate includes a substrate and a gate electrode, a gate insulating layer, a channel layer, an insulating layer, and a passivation layer sequentially formed on the surface of the substrate. An oxide semiconductor layer that forms a channel layer and a plurality of first IPS electrodes that are spaced from the oxide semiconductor layer are provided on the gate insulating layer. The insulating layer covers the oxide semiconductor layer and the plurality of first IPS electrodes. The passivation layer covers the channel layer and is formed with trenches. The trenches are located on a side of each of the first IPS electrode and extending to the gate insulation layer. Second IPS electrodes are formed on the passivation layer and corresponding to the first IPS electrodes and are connected to the first IPS electrodes.
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公开(公告)号：US10416507B2
公开(公告)日：2019-09-17
申请号：US16134934
申请日：2018-09-18
发明人： Xianwang Wei , Yang Liu
IPC分类号： G02F1/1343 , G02F1/1333 , H01L27/12
摘要： An array substrate includes a substrate and a gate electrode, a gate insulating layer, a channel layer, an insulating layer, and a passivation layer sequentially formed on the surface of the substrate. An oxide semiconductor layer that forms a channel layer and a plurality of first IPS electrodes that are spaced from the oxide semiconductor layer are provided on the gate insulating layer. The insulating layer covers the oxide semiconductor layer and the plurality of first IPS electrodes. The passivation layer covers the channel layer and is formed with trenches. The trenches are located on a side of each of the first IPS electrode and extending to the gate insulation layer. Second IPS electrodes are formed on the passivation layer and corresponding to the first IPS electrodes and are connected to the first IPS electrodes.
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公开(公告)号：US10151954B2
公开(公告)日：2018-12-11
申请号：US15510231
申请日：2017-01-13
发明人： Xianwang Wei , Yang Liu
IPC分类号： G02F1/1343 , G02F1/1333 , G02F1/1335
摘要： The present application discloses an array substrate and its fabricating method thereof, the array substrate including a substrate, a gate electrode, a gate insulating layer, a channel layer, an insulating layer, and a passivation layer sequentially formed on the surface of the substrate; an oxide semiconductor layer constituting the channel layer and a plurality of first IPS electrodes spaced apart from the oxide semiconductor layer is further provided on the gate insulating layer; the insulating layer covers the oxide semiconductor layer and the oxide semiconductor layer and the plurality of first IPS electrodes; the passivation layer covers the channel layer and formed with trenches, the trenches located on a side of each of the first IPS electrode and extending to the gate insulation layer; a second IPS electrodes corresponding to the first IPS electrodes and connected to the first IPS electrodes are formed on the passivation layer.
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