Invention Grant
- Patent Title: Fan-out wafer level packaging structure
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Application No.: US15628488Application Date: 2017-06-20
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Publication No.: US10418299B2Publication Date: 2019-09-17
- Inventor: Chung-Hsuan Tsai , Chuehan Hsieh
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Agent Cliff Z. Liu
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/00 ; H01L23/538 ; H01L25/065 ; H01L23/495 ; H01L21/56 ; H01L21/48

Abstract:
A semiconductor device includes a first die including a first pad and a first passivation layer, a second die including a second pad and a second passivation layer, and an encapsulant surrounding the first die and the second die. Surfaces of the first die are not coplanar with corresponding surfaces of the second die. A dielectric layer covers at least portions of the first passivation layer and the second passivation layer, and further covers the encapsulant between the first die and the second die. The encapsulant has a first surface. The dielectric layer has a second surface adjacent to the first passivation layer, the second passivation layer and the encapsulant, and further has a third surface opposite the second surface. The semiconductor device further includes a redistribution layer electrically connected to the first pad and the second pad and disposed above the third surface of the dielectric layer.
Public/Granted literature
- US20170287738A1 FAN-OUT WAFER LEVEL PACKAGING STRUCTURE Public/Granted day:2017-10-05
Information query
IPC分类: