A display apparatus includes a timing controller configured to generate a single clock control signal comprising a plurality of ON-control pulses and a plurality of OFF-control pulses, a gate clock generator configured to generate a plurality of clock signals based on the single clock control signal, ON-periods of the plurality of clock signals starting in response to an ON-control pulse among the ON-control pulses and OFF-periods of the plurality of clock signals starting in response to an OFF-control pulse among the OFF-control pulses, a gate driver comprising a plurality of shift registers which generates a plurality of gate signals based on the plurality of clock signals, and a display panel comprising a display area in which a plurality of pixels is arranged and a peripheral area in which the plurality of shift registers is arranged.