- 专利标题: Method and apparatus for adaptively reducing artifacts in block-coded video
-
申请号: US15271152申请日: 2016-09-20
-
公开(公告)号: US10440395B2公开(公告)日: 2019-10-08
- 发明人: Jorge E. Caviedes , Mahesh M. Subedar , Khasim S. Dudekula
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Green, Howard & Mughal LLP.
- 主分类号: H04N19/86
- IPC分类号: H04N19/86 ; H04N19/80 ; H04N19/117 ; H04N19/136 ; H04N19/44 ; H04N19/176 ; H04N19/14 ; H04N19/172 ; H04N19/182 ; H04W84/18
摘要:
Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
公开/授权文献
信息查询