Invention Grant
- Patent Title: Low resistance interconnect
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Application No.: US15769432Application Date: 2015-12-26
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Publication No.: US10446439B2Publication Date: 2019-10-15
- Inventor: Philip Yashar , Gokul Malyavanatham
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- International Application: PCT/US2015/000370 WO 20151226
- International Announcement: WO2017/111814 WO 20170629
- Main IPC: H01L21/285
- IPC: H01L21/285 ; H01L23/532 ; H01L21/768

Abstract:
An embodiment includes an apparatus comprising: a transistor formed on a substrate; and a metal interconnect formed in a dielectric layer above the transistor, wherein: the interconnect comprises a copper layer and a barrier layer that separates the copper layer from the dielectric layer, and the barrier layer comprises tantalum and niobium. Other embodiments are described herein.
Public/Granted literature
- US20180301373A1 LOW RESISTANCE INTERCONNECT Public/Granted day:2018-10-18
Information query
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