Invention Grant
- Patent Title: Stacked semiconductor dies including inductors and associated methods
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Application No.: US16128414Application Date: 2018-09-11
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Publication No.: US10446527B2Publication Date: 2019-10-15
- Inventor: Eiichi Nakano
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L25/065 ; H01L25/00 ; H01L23/522

Abstract:
Semiconductor devices, systems including semiconductor devices, and methods of making and operating semiconductor devices. Such semiconductor devices can comprise a substrate, a first die mounted to the substrate, and a second die mounted to the first die in an offset position. The first die having first inductors at a first active side of the first die, the second inductors at a second active side of the second die, and a least one first inductor is proximate and inductively coupled to a second inductor. First interconnects electrically couple the substrate to the first die, and second interconnects electrically couple the second die to the substrate. The first interconnects extend from an upper surface of the substrate to the first active side, and the second interconnects extend from the second active side to the lower surface of the substrate.
Public/Granted literature
- US20190067253A1 STACKED SEMICONDUCTOR DIES INCLUDING INDUCTORS AND ASSOCIATED METHODS Public/Granted day:2019-02-28
Information query
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