公开(公告)号：US12243610B2

公开(公告)日：2025-03-04

申请号：US17821676

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Kunal R. Parekh ,  Brent Keeth ,  Eiichi Nakano ,  Amy Rae Griffin

IPC: G11C29/00 ,  G11C7/10 ,  G11C29/56

Abstract: Methods, systems, and devices for memory with parallel main and test interfaces are described. A memory die may be configured with parallel interfaces that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack). For example, a memory die may include a first set of one or more contacts that support communicating signaling with or via another memory die in a multiple-die stack. The memory die may also include a second set of one or more contacts that support probing for pre-assembly evaluations, which may be electrically isolated from the first set of contacts. By implementing such parallel interfaces, evaluation operations may be performed using the second set of contacts without damaging the first set of contacts, which may improve capabilities for supporting a multiple-die stack in a memory device.

公开(公告)号：US20240203827A1

公开(公告)日：2024-06-20

申请号：US18416579

申请日：2024-01-18

Applicant: Micron Technology, Inc.

Inventor： Xiaopeng Qu ,  Hyunsuk Chun ,  Eiichi Nakano

IPC: H01L23/473 ,  H01L21/48 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/4735 ,  H01L21/4871 ,  H01L23/3672 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50

Abstract: Semiconductor packages and/or assemblies having microchannels, a microchannel module, and/or a microfluidic network for thermal management, and associated systems and methods, are disclosed herein. The semiconductor package and/or assembly can include a substrate integrated with a microchannel and a coolant disposed within the microchannel to dissipate heat from a memory device and/or a logic device of the semiconductor package and/or assembly. The microchannel can be configured beneath the memory device and/or the logic device.

公开(公告)号：US20240194287A1

公开(公告)日：2024-06-13

申请号：US18525403

申请日：2023-11-30

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth ,  Kunal R. Parekh ,  Eiichi Nakano ,  Amy Rae Griffin

IPC: G11C29/52 ,  G11C29/02

CPC classification number: G11C29/52 ,  G11C29/022 ,  G11C29/025

Abstract: Methods, systems, and devices for repair techniques for coupled host and memory dies are described. For example, to distribute memory access circuitry among multiple semiconductor dies of a stack, a first die may include a set of one or more memory arrays and a first portion of circuitry configured to access the set of memory arrays, and a second die may include a second portion of circuitry configured to access the set of memory arrays. The second portion of the circuitry (e.g., of the second die) may be configured to support various repair techniques for operations with the set of memory arrays, including techniques in response to column failures or serialization failures associated with the first die, or in response to contact or other interconnection failures with or between the first die and the second die, among other techniques that may be differentiated based on an attribution of error conditions.

公开(公告)号：US11817420B2

公开(公告)日：2023-11-14

申请号：US17379568

申请日：2021-07-19

Applicant: Micron Technology, Inc.

Inventor： Chia Jung Hsu ,  Eiichi Nakano

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/80 ,  H01L24/05 ,  H01L25/0657 ,  H01L2224/05647 ,  H01L2224/8012 ,  H01L2224/80948 ,  H01L2225/06541

Abstract: A stacked semiconductor device and systems and methods for producing the same are disclosed here. In some embodiments, the method includes aligning a first array of bond pads on an upper surface of a first semiconductor substrate with a second array of bond pads on a lower surface of a second semiconductor substrate. The method then includes annealing the stacked semiconductor device to bond the upper surface of the first semiconductor substrate to the lower surface of the second semiconductor substrate. The annealing results in at least one void between the upper surface and the lower surface that includes a layer of diffused metal. The layer of diffused metal extends from a first individual bond pad towards a second individual bond pad and forms an electrical or thermal short. The method then includes exposing the stacked semiconductor device to microwave radiation to excite a chemical constituent present in the void.

公开(公告)号：US20220375902A1

公开(公告)日：2022-11-24

申请号：US17817690

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Randon K. Richards ,  Aparna U. Limaye ,  Dong Soon Lim ,  Chan H. Yoo ,  Bret K. Street ,  Eiichi Nakano ,  Shijian Luo

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/552 ,  H01L23/64 ,  H01L21/78 ,  H01L21/66 ,  H01L25/00 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/48

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.

公开(公告)号：US11380665B2

公开(公告)日：2022-07-05

申请号：US16553698

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano ,  Shiro Uchiyama

IPC: G11C7/02 ,  H01L25/18 ,  H01L25/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/538

Abstract: A semiconductor device assembly, including an interposer comprising a glass material, a semiconductor die comprising a proximity coupling on a side of the interposer, and at least one other semiconductor die comprising a proximity coupling configured for communicating signals with the proximity coupling of the semiconductor die, on an opposing side of the interposer. The assembly may optionally be configured for optical signal communication with higher level packaging. Semiconductor device packages, systems and methods of operation are also disclosed.

公开(公告)号：US20220077098A1

公开(公告)日：2022-03-10

申请号：US17456066

申请日：2021-11-22

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano ,  Mark E. Tuttle

IPC: H01L23/00 ,  H01L25/065

Abstract: An anisotropic conductive film (ACF) is formed with an ordered array of discrete regions that include a conductive carbon-based material. The discrete regions, which may be formed at small pitch, are embedded in at least one adhesive dielectric material. The ACF may be used to mechanically and electrically interconnect conductive elements of initially-separate semiconductor dice in semiconductor device assemblies. Methods of forming the ACF include forming a precursor structure with the conductive carbon-based material and then joining the precursor structure to a separately-formed structure that includes adhesive dielectric material to be included in the ACF. Sacrificial materials of the precursor structure may be removed and additional adhesive dielectric material formed to embed the discrete regions with the conductive carbon-based material in the adhesive dielectric material of the ACF.

公开(公告)号：US20220028820A1

公开(公告)日：2022-01-27

申请号：US17490224

申请日：2021-09-30

Applicant: Micron Technology, Inc.

Inventor： Mark E. Tuttle ,  John F. Kaeding ,  Owen R. Fay ,  Eiichi Nakano ,  Shijian Luo

IPC: H01L23/00

Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate. The method may include passing electrical current through the plurality of interconnects.

公开(公告)号：US20210407889A1

公开(公告)日：2021-12-30

申请号：US16990943

申请日：2020-08-11

Applicant: Micron Technology, Inc.

Inventor： Xiaopeng Qu ,  Hyunsuk Chun ,  Eiichi Nakano

IPC: H01L23/473 ,  H01L25/065 ,  H01L25/18 ,  H01L23/367 ,  H01L21/48 ,  H01L25/00

Abstract: Semiconductor packages and/or assemblies having microchannels, a microchannel module, and/or a microfluidic network for thermal management, and associated systems and methods, are disclosed herein. The semiconductor package and/or assembly can include a substrate integrated with a microchannel and a coolant disposed within the microchannel to dissipate heat from a memory device and/or a logic device of the semiconductor package and/or assembly. The microchannel can be configured beneath the memory device and/or the logic device.

公开(公告)号：US11139262B2

公开(公告)日：2021-10-05

申请号：US16270112

申请日：2019-02-07

Applicant: Micron Technology, Inc.

Inventor： Mark E. Tuttle ,  John F. Kaeding ,  Owen R. Fay ,  Eiichi Nakano ,  Shijian Luo

IPC: H01L21/76 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate. The method may include passing electrical current through the plurality of interconnects.