- 专利标题: Advanced node cost reduction by ESD interposer
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申请号: US15743996申请日: 2015-09-14
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公开(公告)号: US10446541B2公开(公告)日: 2019-10-15
- 发明人: Georg Seidemann , Christian Geissler , Klaus Reingruber
- 申请人: Intel IP Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel IP Corporation
- 当前专利权人: Intel IP Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwabe, Williamson & Wyatt, P.C.
- 国际申请: PCT/US2015/049923 WO 20150914
- 国际公布: WO2017/048219 WO 20170323
- 主分类号: H01L23/48
- IPC分类号: H01L23/48 ; H01L27/02 ; H01L23/60 ; H01L23/00 ; H01L25/065 ; H01L25/18 ; H01L49/02 ; H01L25/10 ; H01L23/14 ; H01L23/498
摘要:
An apparatus including an electrostatic discharge circuit including a first circuit portion coupled beneath a die contact pad of an integrated circuit die and a second circuit portion in an interposer separate from the integrated circuit die, the interposer including a first contact point coupled to the contact pad of the integrated circuit die and a second contact point operable for connection to an external source. A method including forming an integrated circuit die including a first electrostatic discharge structure beneath a contact pad of the die; and coupling the die to an interposer including an interposer contact and a second electrostatic discharge structure, wherein a signal at the contact pad of the die is operable to be routed through the interposer.
公开/授权文献
- US20180204831A1 ADVANCED NODE COST REDUCTION BY ESD INTERPOSER 公开/授权日:2018-07-19