Invention Grant
- Patent Title: Increasing granularity of dirty bit information in hardware assisted memory management systems
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Application No.: US15708063Application Date: 2017-09-18
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Publication No.: US10452559B2Publication Date: 2019-10-22
- Inventor: Benjamin C. Serebrin , Bhavesh Mehta
- Applicant: VMware, Inc.
- Applicant Address: US CA Palo Alto
- Assignee: VMware, Inc.
- Current Assignee: VMware, Inc.
- Current Assignee Address: US CA Palo Alto
- Agency: Patterson + Sheridan, LLP
- Main IPC: G06F12/1036
- IPC: G06F12/1036 ; G06F12/10

Abstract:
In a computer system having virtual machines, one or more unused bits of a guest physical address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, dirty bit information can be provided at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, dirty bit information can be provided at a granularity that is 1/(2M)-th of a memory page.
Public/Granted literature
- US20180004679A1 INCREASING GRANULARITY OF DIRTY BIT INFORMATION IN HARDWARE ASSISTED MEMORY MANAGEMENT SYSTEMS Public/Granted day:2018-01-04
Information query
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