Invention Grant
- Patent Title: Logic die and other components embedded in build-up layers
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Application No.: US15346568Application Date: 2016-11-08
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Publication No.: US10453799B2Publication Date: 2019-10-22
- Inventor: Deepak V. Kulkarni , Russell K. Mortensen , John S. Guzek
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/50 ; H01L23/498 ; H01L23/00 ; H01L21/48 ; H01L21/768 ; H01L23/48 ; H01L23/485 ; H01L25/065 ; H01L25/16 ; H01L25/00 ; H01L49/02

Abstract:
Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate including a plurality of build-up layers, such as bumpless build-up layer (BBUL). In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.
Public/Granted literature
- US20170125351A1 LOGIC DIE AND OTHER COMPONENTS EMBEDDED IN BUILD-UP LAYERS Public/Granted day:2017-05-04
Information query
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