公开(公告)号：US20170125351A1

公开(公告)日：2017-05-04

申请号：US15346568

申请日：2016-11-08

Applicant: INTEL CORPORATION

Inventor： Deepak V. Kulkarni ,  Russell K. Mortensen ,  John S. Guzek

IPC: H01L23/538 ,  H01L49/02 ,  H01L21/768 ,  H01L23/48 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L28/40 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2224/92224 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate including a plurality of build-up layers, such as bumpless build-up layer (BBUL). In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.

公开(公告)号：US10453799B2

公开(公告)日：2019-10-22

申请号：US15346568

申请日：2016-11-08

Applicant: INTEL CORPORATION

Inventor： Deepak V. Kulkarni ,  Russell K. Mortensen ,  John S. Guzek

IPC: H01L23/538 ,  H01L21/50 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/768 ,  H01L23/48 ,  H01L23/485 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L49/02

Abstract: Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate including a plurality of build-up layers, such as bumpless build-up layer (BBUL). In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.

公开(公告)号：US20160151850A1

公开(公告)日：2016-06-02

申请号：US15017398

申请日：2016-02-05

Applicant: Intel Corporation

Inventor： Deepak V. Kulkarni ,  Carl L. Deppisch ,  Leonel R. Arana ,  Gregory S. Constable ,  Sriram Srinivasan

IPC: B23K1/00 ,  B23K1/20 ,  H01L23/367

CPC classification number: B23K1/0016 ,  B23K1/20 ,  B23K1/203 ,  B23K3/085 ,  H01L23/3675 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/16251 ,  Y10T428/12222

Abstract: Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.

Abstract translation: 形成封装结构的方法和相关结构包括在IHS的阻焊剂开口位置上形成低熔点焊料材料，从而在非SRO保护区域内形成密封剂; 将IHS连接到密封剂上，并固化密封剂，其中在IHS和低熔点焊料材料之间形成焊接接头。

公开(公告)号：US09808875B2

公开(公告)日：2017-11-07

申请号：US15017398

申请日：2016-02-05

Applicant: Intel Corporation

Inventor： Deepak V. Kulkarni ,  Carl L. Deppisch ,  Leonel R. Arana ,  Gregory S. Constable ,  Sriram Srinivasan

IPC: B23K31/00 ,  B23K31/02 ,  B23K1/00 ,  B23K3/08 ,  B23K1/20 ,  H01L23/367

CPC classification number: B23K1/0016 ,  B23K1/20 ,  B23K1/203 ,  B23K3/085 ,  H01L23/3675 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/16251 ,  Y10T428/12222

Abstract: Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.

公开(公告)号：US09496211B2

公开(公告)日：2016-11-15

申请号：US13684110

申请日：2012-11-21

Applicant: INTEL CORPORATION

Inventor： Deepak V. Kulkarni ,  Russell K. Mortensen ,  John S. Guzek

IPC: H01L23/498 ,  H01L21/50 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L28/40 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2224/92224 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate including a plurality of build-up layers, such as bumpless build-up layer (BBUL). In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.

Abstract translation: 本公开的实施例涉及包装组件，以及用于形成包装组件和包含包装组件的系统的方法。 封装组件可以包括包括多个堆积层的衬底，例如无扰性积聚层（BBUL）。 在各种实施例中，电路由特征可以设置在衬底的外表面上。 在各种实施例中，主逻辑管芯和第二管芯或电容器可以嵌入在多个堆积层中。 在各种实施例中，可以在多个积层中定义电路径，以便绕过主逻辑管芯来路由第二管芯或电容器之间的电功率或接地信号与电路径特征。