Invention Grant
- Patent Title: Power optimization mechanisms for framers by serializing frame alignment processes for multiple lanes
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Application No.: US15389165Application Date: 2016-12-22
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Publication No.: US10455501B2Publication Date: 2019-10-22
- Inventor: Francesco Caggioni , Dimitrios Giannakopoulos
- Applicant: Applied Micro Circuits Corporation
- Applicant Address: US MA Lowell
- Assignee: MACOM Connectivity Solutions, LLC
- Current Assignee: MACOM Connectivity Solutions, LLC
- Current Assignee Address: US MA Lowell
- Main IPC: H04W52/02
- IPC: H04W52/02 ; H04L1/00 ; H04L7/04 ; H04W24/02 ; H04W56/00

Abstract:
System and method of frame alignment at a receiver with power optimization mechanisms. A framer at the receiver is configured to process data streams from multiple physical lanes and/or multiple channels serially. The receiver may include multiple framers that process different sets of data streams in parallel. A framer may enter a power reduction mode after all the channels associated therewith have achieved frame alignment. The framer can be restarted to perform frame alignment processes on a particular channel responsive to an indication that the channel transitions to an out-of-frame state. The “out-of-frame” indication may be generated by a forward error correction (FEC) decoder when it detects an excessive number of uncorrectable errors in the channel.
Public/Granted literature
- US20180184373A1 POWER OPTIMIZATION MECHANISMS FOR FRAMERS BY SERIALIZING FRAME ALIGNMENT PROCESSES FOR MULTIPLE LANES Public/Granted day:2018-06-28
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