A computer performing a transient vectorless power analysis of a multi-clock domain integrated circuit (IC) design may execute a scheduling cycle based on the dominant clock frequency and schedule events based on comparing instance clock frequencies with the dominant clock frequency. If the instance clock frequency matches the dominant clock frequency, the computer may schedule a single event per scheduling cycle for the sequential circuit devices driven by the respective instance clocks. If the instance clock frequency is faster than the dominant clock frequency, the computer may schedule number of events per scheduling cycle based on the ratio of the instance clock frequency to the dominant clock frequency. If the instance clock frequency is less than the dominant clock frequency, the computer may schedule a single event per scheduling cycle if the computer determines that there is a triggering edge of the instance clock within the scheduling cycle.