Invention Grant
- Patent Title: Methods of forming vertical field effect transistors with self-aligned contacts and the resulting structures
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Application No.: US15994392Application Date: 2018-05-31
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Publication No.: US10461186B1Publication Date: 2019-10-29
- Inventor: John H. Zhang , Ruilong Xie , Mahender Kumar
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Gibb & Riley, LLC
- Agent Anthony J. Canale
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L21/762 ; H01L29/06

Abstract:
Disclosed are methods wherein vertical field effect transistor(s) (VFET(s)) and isolation region(s) are formed on a substrate. Each VFET includes a fin extending vertically between source/drain regions, a spacer layer and a gate around the fin, and a source/drain sidewall spacer around an upper source/drain region. Optionally, a gate sidewall spacer is adjacent to the gate at a first end of the VFET. An isolation region is adjacent to the gate at a second end and opposing sides of the VFET and extends into the substrate. Contacts are formed including a lower source/drain contact (which is adjacent to the first end of the VFET and is self-aligned if the optional gate sidewall spacer is present) and a self-aligned gate contact (which extends into the isolation region at the second end of the VFET and contacts a side surface of the gate). Also disclosed are structures formed according to the methods.
Information query
IPC分类: