公开(公告)号：US11374111B2

公开(公告)日：2022-06-28

申请号：US16743293

申请日：2020-01-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Chun-Chen Yeh ,  Qing Liu ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L21/768 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165

Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

公开(公告)号：US10998422B2

公开(公告)日：2021-05-04

申请号：US16730712

申请日：2019-12-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Laertis Economikos ,  Ruilong Xie

IPC: H01L21/70 ,  H01L29/66 ,  H01L27/02 ,  H01L21/8238

Abstract: At least one method, apparatus and system disclosed herein involves adjusting for a misalignment of a gate cut region with respect to semiconductor processing. A plurality of fins are formed on a semiconductor substrate. A gate region is formed over a portion of the fins. The gate region comprises a first dummy gate and a second dummy gate. A gate cut region is formed over the first dummy gate. A conformal fill material is deposited into the gate cut region. At least one subsequent processing step is performed.

公开(公告)号：US20210043727A1

公开(公告)日：2021-02-11

申请号：US16534317

申请日：2019-08-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: A gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes nanosheets, a gate around center portions of the nanosheets, and inner spacers aligned below end portions. The nanosheet end portions are tapered from the source/drain regions to the gate and the inner spacers are tapered from the gate to the source/drain regions. Each inner spacer includes: a first spacer layer, which has a uniform thickness and extends laterally from the gate to an adjacent source/drain region; a second spacer layer, which fills the space between a planar top surface of the first spacer layer and a tapered end portion of the nanosheet above; and, for all but the lowermost inner spacers, a third spacer layer, which is the same material as the second spacer layer and which fills the space between a planar bottom surface of the first spacer layer and a tapered end portion of the nanosheet below.

公开(公告)号：US10892338B2

公开(公告)日：2021-01-12

申请号：US16169269

申请日：2018-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Jae Gon Lee

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scaled gate contact and source/drain cap and methods of manufacture. The structure includes: a gate structure comprising an active region; source and drain contacts adjacent to the gate structure; a capping material over the source and drain contacts; a gate contact formed directly above the active region of the gate structure and over the capping material; a U-shape dielectric material around the gate contact, above the source and drain contacts; and a contact in direct electrical contact to the source and drain contacts.

公开(公告)号：US10825741B2

公开(公告)日：2020-11-03

申请号：US16196413

申请日：2018-11-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L27/092

Abstract: One illustrative IC product disclosed herein includes an isolation structure that separates a fin into a first fin portion and a second fin portion, an epi semiconductor material positioned on the first fin portion in a source/drain region of a transistor device, wherein a lateral gap is present between a first sidewall of the epi semiconductor material and a second sidewall of the SDB isolation structure, and a conductive source/drain structure that is conductively coupled to the epi semiconductor material, wherein a gap portion of the conductive source/drain structure is positioned in the gap and physically contacts the first sidewall and the second sidewall.

公开(公告)号：US10804398B2

公开(公告)日：2020-10-13

申请号：US16160701

申请日：2018-10-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/66

Abstract: A device including source-drain epitaxy contacts with a trench silicide (TS) liner wrapped around the source-drain contacts, and method of production thereof. Embodiments include a device having a gate structure formed over a substrate; source-drain epitaxy contacts including a trench silicide (TS) liner covering the source-drain epitaxy contacts; TS contacts formed on the TS liner over the source-drain epitaxy contacts; and a dielectric pillar disposed in a TS cut between the source-drain epitaxy contacts. The TS liner wraps around the source-drain epitaxy contacts, including bottom negatively tapered surfaces of the source-drain epitaxy contacts.

公开(公告)号：US20200286900A1

公开(公告)日：2020-09-10

申请号：US16295485

申请日：2019-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Randy W. Mann ,  Bipul C. Paul ,  Julien Frougier ,  Ruilong Xie

IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

Abstract: Structures and static random access memory bit cells including complementary field effect transistors and methods of forming such structures and bit cells. A first complementary field-effect transistor has a first storage nanosheet transistor, a second storage nanosheet transistor stacked over the first storage nanosheet transistor, and a first gate electrode shared by the first storage nanosheet transistor and the second storage nanosheet transistor. A second complementary field-effect transistor has a third storage nanosheet transistor, a fourth storage nanosheet transistor stacked over the third storage nanosheet transistor, and a second gate electrode shared by the third storage nanosheet transistor and the fourth storage nanosheet transistor. The first gate electrode and the second gate electrode are arranged in a spaced arrangement along a longitudinal axis. All gate electrodes of the SRAM bitcell may be arranged in a 1CPP layout.

公开(公告)号：US10763342B2

公开(公告)日：2020-09-01

申请号：US16216356

申请日：2018-12-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/8234

Abstract: A method is presented for forming equal thickness gate spacers for a CMOS (complementary metal oxide semiconductor) device, the method includes forming a PFET (p-type field effect transistor) device and an NFET (n-type field effect transistor) device each including gate masks formed over dummy gates, forming PFET epi growth regions between the dummy gates of the PFET device, forming NFET epi growth regions between the dummy gates of the NFET device, depositing a nitride liner and an oxide over the PFET and NFET epi growth regions, the nitride liner and oxide extending up to the gate masks, and removing the dummy gates and the gate masks to form HKMGs (high-k metal gates) between the PFET and NFET epi growth regions.

公开(公告)号：US10749031B2

公开(公告)日：2020-08-18

申请号：US15273778

申请日：2016-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/45 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/285

Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.

公开(公告)号：US10734525B2

公开(公告)日：2020-08-04

申请号：US15920886

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Christopher M. Prindle ,  Nigel G. Cave

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

Abstract: The disclosure relates to gate-all-around (GAA) transistors with a spacer support, and related methods. A GAA transistor according to embodiments of the disclosure includes: at least one semiconductor channel structure extending between a source terminal and a drain terminal; a spacer support having a first portion thereof positioned underneath and a second portion thereof positioned alongside a first portion of the at least one semiconductor channel structure; and a gate metal surrounding a second portion of the at least one semiconductor channel structure between the source and drain terminals; wherein the spacer support is positioned between the gate metal and the source or drain terminal.