Invention Grant
- Patent Title: Method of manufacturing integrated circuit using encapsulation during an etch process
-
Application No.: US16107543Application Date: 2018-08-21
-
Publication No.: US10461251B2Publication Date: 2019-10-29
- Inventor: Sanjeev Aggarwal , Sarin A. Deshpande , Kerry Joseph Nagel
- Applicant: Everspin Technologies, Inc.
- Applicant Address: US AZ Chandler
- Assignee: EVERSPIN TECHNOLOGIES, INC.
- Current Assignee: EVERSPIN TECHNOLOGIES, INC.
- Current Assignee Address: US AZ Chandler
- Agency: Bookoff McAndrews, PLLC
- Main IPC: H01L43/12
- IPC: H01L43/12 ; H01L27/22
Abstract:
A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.
Public/Granted literature
- US20190103554A1 METHOD OF MANUFACTURING INTEGRATED CIRCUIT USING ENCAPSULATION DURING AN ETCH PROCESS Public/Granted day:2019-04-04
Information query
IPC分类:
