Invention Grant
- Patent Title: Multi-stage amplifier circuit with zero and pole inserted by compensation circuits
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Application No.: US15912448Application Date: 2018-03-05
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Publication No.: US10469037B2Publication Date: 2019-11-05
- Inventor: Sung-Han Wen , Kuan-Ta Chen
- Applicant: MEDIATEK INC.
- Applicant Address: TW Hsin-Chu
- Assignee: MEDIATEK INC.
- Current Assignee: MEDIATEK INC.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Main IPC: H03F1/14
- IPC: H03F1/14 ; H03F1/42 ; H03F1/08 ; H03F3/45 ; H03F1/34 ; H03F3/21
Abstract:
An amplifier circuit has a multi-stage amplifier, a compensation capacitor, and compensation circuits. The multi-stage amplifier has amplifiers cascaded between an input port and an output port of the multi-stage amplifier. The amplifiers include at least a first-stage amplifier, a second-stage amplifier and a third-stage amplifier. The compensation capacitor is coupled between the output port of the multi-stage amplifier and an output port of the first-stage amplifier. The compensation circuits include a first compensation circuit and a second compensation circuit. The first compensation circuit is coupled to the output port of the first-stage amplifier. The second compensation circuit is coupled to an output port of the second-stage amplifier.
Public/Granted literature
- US20180309416A1 MULTI-STAGE AMPLIFIER CIRCUIT WITH ZERO AND POLE INSERTED BY COMPENSATION CIRCUITS Public/Granted day:2018-10-25
Information query
IPC分类:
