An electronic device includes a memory and a system on chip (SoC). The memory device includes a first memory cell area assigned to a first channel and a second memory cell area assigned to a second channel. The SoC includes a first processing unit and a second processing unit. The first processing unit is configured to transmit a first command for accessing the first memory cell area to the memory device through the first channel. The second processing unit is configured to transmit a second command for accessing the second memory cell area to the memory device through the second channel. The memory device is configured such that a bandwidth of the first channel and a bandwidth of the second channel are different from each other.