A circuit includes a ring oscillator and a state capture register to receive a multi-bit state of the ring oscillator captured upon occurrence of an edge of input periodic signal. The circuit also includes an edge-phase detector to assert an edge detect high signal in response to a first reference clock derived from the ring oscillator being high upon occurrence of the edge of the input periodic signal and to assert an edge detect low signal in response to the first reference clock derived from the ring oscillator being low upon occurrence of the edge of the input periodic signal. A first register receives data from the state capture register upon occurrence of one of a rising or falling edge of a second clock derived from the ring oscillator.