Invention Grant
- Patent Title: Latency buffer circuit with adaptable time shift
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Application No.: US15846560Application Date: 2017-12-19
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Publication No.: US10484165B2Publication Date: 2019-11-19
- Inventor: Rupesh Singh , Ankur Bal
- Applicant: STMicroelectronics International N.V.
- Applicant Address: NL Schiphol
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Schiphol
- Agency: Crowe & Dunlevy
- Main IPC: H04L7/00
- IPC: H04L7/00

Abstract:
Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.
Public/Granted literature
- US20190190688A1 LATENCY BUFFER CIRCUIT WITH ADAPTABLE TIME SHIFT Public/Granted day:2019-06-20
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