Invention Grant
- Patent Title: Partially written superblock treatment
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Application No.: US15677736Application Date: 2017-08-15
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Publication No.: US10552254B2Publication Date: 2020-02-04
- Inventor: Dheeraj Srinivasan , Ali Mohammadzadeh
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G11C11/56 ; H03M13/37

Abstract:
The present disclosure relates to partially written superblock treatment. An example apparatus includes a memory device operable as a multiplane memory resource including blocks organized as superblocks. The memory device is configured to maintain, internal to the memory device, included in a status of an open superblock, a page indicator corresponding to a last written page of the open superblock. The memory device is further configured, responsive to receipt, from a controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request.
Public/Granted literature
- US20190056989A1 PARTIALLY WRITTEN SUPERBLOCK TREATMENT Public/Granted day:2019-02-21
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