Invention Grant
- Patent Title: Apparatuses and methods for reading memory cells
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Application No.: US16138256Application Date: 2018-09-21
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Publication No.: US10553594B2Publication Date: 2020-02-04
- Inventor: Yasushi Matsubara
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G11C11/22
- IPC: G11C11/22 ; H01L27/11502 ; H01L27/10 ; H01L49/02 ; G11C5/14

Abstract:
Apparatuses and methods for reading memory cells are described. An example method includes sharing a first voltage to increase a voltage of a first sense line coupled to a first capacitor plate of a ferroelectric capacitor of a memory cell, sharing a second voltage to decrease a voltage of a second sense line coupled to a second capacitor plate of the ferroelectric capacitor of the memory cell, sharing a third voltage to increase the voltage of the second sense line, and sharing a fourth voltage to decrease the voltage of the first sense line. A voltage difference between the first sense line and the second sense line that results from the voltage sharing is amplified, wherein the voltage difference is based at least in part on a polarity of the ferroelectric capacitor.
Public/Granted literature
- US20190051657A1 APPARATUSES AND METHODS FOR READING MEMORY CELLS Public/Granted day:2019-02-14
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