公开(公告)号：US11487346B2

公开(公告)日：2022-11-01

申请号：US16890819

申请日：2020-06-02

Applicant: Micron Technology, Inc.

Inventor： Ki-Jun Nam ,  Yantao Ma ,  Yasushi Matsubara ,  Takamasa Suzuki

IPC: G06F1/00 ,  G06F1/3296 ,  G06F1/3234 ,  G11C11/22

Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.

公开(公告)号：US11276455B1

公开(公告)日：2022-03-15

申请号：US17082964

申请日：2020-10-28

Applicant: Micron Technology, Inc.

Inventor： Takamasa Suzuki ,  Yasushi Matsubara ,  John D. Porter ,  Ki-Jun Nam

IPC: G06F1/26 ,  G11C11/4072 ,  G11C11/4074 ,  G11C7/06 ,  G11C5/06 ,  G11C11/4091

Abstract: A memory device is provided. The memory device includes a memory bank configured to store data in one or more memory cells. The memory device further includes a sense amplifier and associated circuitry configured to detect a first threshold representative of a first external voltage ramping down during a power off of the memory device, and one or more switches triggered via the sense amplifier and associated circuitry to provide for a power off sequence for the memory bank based on using a second external voltage ramping down during the power off of the memory device.

公开(公告)号：US20210407556A1

公开(公告)日：2021-12-30

申请号：US16916612

申请日：2020-06-30

Applicant: Micron Technology, Inc.

Inventor： Yasushi Matsubara ,  Yusuke Jono ,  Donald Martin Morgan ,  Nobuo Yamamoto

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/18 ,  G11C7/20

Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

公开(公告)号：US11211109B2

公开(公告)日：2021-12-28

申请号：US17103521

申请日：2020-11-24

Applicant: Micron Technology, Inc.

Inventor： Yasushi Matsubara

IPC: G11C11/22 ,  G11C11/4074 ,  G11C11/4091 ,  G06F12/14 ,  G11C8/08 ,  G11C16/26 ,  G11C16/08 ,  G11C16/10

Abstract: Methods, systems, and devices for protecting stored data in a memory device are described. In one example, a memory device may include a set of memory cells coupled with a digit line and a plate line. A method of operating the memory device may include performing an access operation on a selected memory cell of the set of memory cells, and performing an equalization operation on a non-selected memory cell of the plurality of memory cells based on performing the access operation. The equalization operation may include applying an equal voltage to opposite terminals of the non-selected memory cell via the digit line and the plate line, which may allow built-up charge, such as leakage charge resulting from the access operation, to dissipate. Such an equalization operation may reduce a likelihood of memory loss in non-selected memory cells after access operations.

公开(公告)号：US20200185020A1

公开(公告)日：2020-06-11

申请号：US16793889

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22

Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.

公开(公告)号：US20190325934A1

公开(公告)日：2019-10-24

申请号：US15958973

申请日：2018-04-20

Applicant: Micron Technology, Inc.

Inventor： Yasushi Matsubara

IPC: G11C11/22 ,  G11C11/4074 ,  G11C11/4091 ,  G11C8/08 ,  G06F12/14

Abstract: Methods, systems, and devices for protecting stored data in a memory device are described. In one example, a memory device may include a set of memory cells coupled with a digit line and a plate line. A method of operating the memory device may include performing an access operation on a selected memory cell of the set of memory cells, and performing an equalization operation on a non-selected memory cell of the plurality of memory cells based on performing the access operation. The equalization operation may include applying an equal voltage to opposite terminals of the non-selected memory cell via the digit line and the plate line, which may allow built-up charge, such as leakage charge resulting from the access operation, to dissipate. Such an equalization operation may reduce a likelihood of memory loss in non-selected memory cells after access operations.

公开(公告)号：US20190311757A1

公开(公告)日：2019-10-10

申请号：US16387220

申请日：2019-04-17

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22

Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.

公开(公告)号：US20190287602A1

公开(公告)日：2019-09-19

申请号：US16269485

申请日：2019-02-06

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22

Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.

公开(公告)号：US10229727B1

公开(公告)日：2019-03-12

申请号：US15919994

申请日：2018-03-13

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22

Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.

公开(公告)号：US20190051657A1

公开(公告)日：2019-02-14

申请号：US16138256

申请日：2018-09-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasushi Matsubara

IPC: H01L27/11502 ,  G11C11/22 ,  H01L49/02 ,  H01L27/10 ,  G11C5/14

CPC classification number: H01L27/11502 ,  G11C5/147 ,  G11C7/12 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C2207/002 ,  H01L27/101 ,  H01L28/55

Abstract: Apparatuses and methods for reading memory cells are described. An example method includes sharing a first voltage to increase a voltage of a first sense line coupled to a first capacitor plate of a ferroelectric capacitor of a memory cell, sharing a second voltage to decrease a voltage of a second sense line coupled to a second capacitor plate of the ferroelectric capacitor of the memory cell, sharing a third voltage to increase the voltage of the second sense line, and sharing a fourth voltage to decrease the voltage of the first sense line. A voltage difference between the first sense line and the second sense line that results from the voltage sharing is amplified, wherein the voltage difference is based at least in part on a polarity of the ferroelectric capacitor.