Invention Grant
- Patent Title: System and method for parallelization of data processing in a processor
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Application No.: US15191257Application Date: 2016-06-23
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Publication No.: US10558466B2Publication Date: 2020-02-11
- Inventor: Mauricio Breternitz , Mayank Daga
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Meyertons Hood Kivlin Kowert and Goetzel PC
- Agent Rory D. Rankin
- Main IPC: G06F9/38
- IPC: G06F9/38

Abstract:
Systems, apparatuses, and methods for adjusting group sizes to match a processor lane width are described. In early iterations of an algorithm, a processor partitions a dataset into groups of data points which are integer multiples of the processing lane width of the processor. For example, when performing a K-means clustering algorithm, the processor determines that a first plurality of data points belong to a first group during a given iteration. If the first plurality of data points is not an integer multiple of the number of processing lanes, then the processor reassigns a first number of data points from the first plurality of data points to one or more other groups. The processor then performs the next iteration with these first number of data points assigned to other groups even though the first number of data points actually meets the algorithmic criteria for belonging to the first group.
Public/Granted literature
- US20170371665A1 SYSTEM AND METHOD FOR PROCESSING DATA IN A COMPUTING SYSTEM Public/Granted day:2017-12-28
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