Invention Grant
- Patent Title: Memory error detection
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Application No.: US15838161Application Date: 2017-12-11
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Publication No.: US10558520B2Publication Date: 2020-02-11
- Inventor: Ian Shaeffer , Craig E. Hampel
- Applicant: Rambus Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Sunnyvale
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/10 ; G06F11/07 ; G06F11/16 ; H03M13/09

Abstract:
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.
Public/Granted literature
- US20180203759A1 Memory Error Detection Public/Granted day:2018-07-19
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