Invention Grant
- Patent Title: Memory system with dynamic calibration using a trim management mechanism
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Application No.: US15981810Application Date: 2018-05-16
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Publication No.: US10566063B2Publication Date: 2020-02-18
- Inventor: Michael Sheperek , Larry J. Koudele , Steve Kientz
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: G11C16/26
- IPC: G11C16/26 ; G06F3/06 ; G11C11/56 ; G11C16/04

Abstract:
A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to iteratively: determine a set of read results based on reading a subset of memory cells according to read levels maintained within optimization trim data, wherein the optimization trim data initially comprises at least one read level in addition to a target trim; calibrate the set of read levels based on the set of read results; and remove the calibrated read levels from the optimization trim data when the calibrated read levels satisfy a calibration condition.
Public/Granted literature
- US20190355426A1 MEMORY SYSTEM WITH DYNAMIC CALIBRATION USING A TRIM MANAGEMENT MECHANISM Public/Granted day:2019-11-21
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