Invention Grant
- Patent Title: Circuit arrangements and methods for performing multiply-and-accumulate operations
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Application No.: US16142406Application Date: 2018-09-26
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Publication No.: US10572225B1Publication Date: 2020-02-25
- Inventor: Ehsan Ghasemi , Elliott Delaye , Ashish Sirasao , Sean Settle
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agent LeRoy D. Maunu
- Main IPC: G06F7/544
- IPC: G06F7/544 ; G06N3/02 ; G06T1/60 ; G06N3/08
Abstract:
A and a request generator circuit is configured to read data elements of a three-dimensional (3-D) input feature map (IFM) from a memory and store a subset of the data elements in one of a plurality of N line buffers. Each line buffer is configured for storage of M data elements. A pixel iterator circuit is coupled to the line buffers and is configured to generate a sequence of addresses for reading the stored data elements from the line buffers based on a sequence of IFM height values and a sequence of IFM width values.
Information query
