Invention Grant
- Patent Title: PCIe lane aggregation over a high speed link
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Application No.: US16267748Application Date: 2019-02-05
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Publication No.: US10572425B2Publication Date: 2020-02-25
- Inventor: Sreenivas Krishnan , Nirmal Raj Saxena
- Applicant: INPHI CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INPHI CORPORATION
- Current Assignee: INPHI CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Ogawa P.C.
- Agent Richard T. Ogawa
- Main IPC: G06F13/40
- IPC: G06F13/40 ; H04L12/64 ; H04L12/66 ; H04Q11/00 ; G06F13/42 ; H04B10/27 ; H04J14/02 ; H04L12/933

Abstract:
A method of operating a computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. Each of rack modules can include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.
Public/Granted literature
- US20190171605A1 PCIE LANE AGGREGATION OVER A HIGH SPEED LINK Public/Granted day:2019-06-06
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