Systems, methods, and apparatus are described. An apparatus provides a clock signal, transmits an address on a second line of the serial bus followed by a read/write bit configured to initiate a read transaction, and delays a pulse in the clock signal after transmitting the read/write bit. The pulse may be delayed for a first duration configured to accommodate a latency associated with a first slave device that is a participant in the read transaction. The apparatus may receive an acknowledgement from the first slave device while the pulse is being transmitted and may receive a first data byte from the first slave device after receiving the acknowledgment. The apparatus may stall the clock signal for a second duration after receiving the first data byte from the first slave device, and receive a second data byte from the first slave device after the acknowledgment.