Invention Grant
- Patent Title: Custom piecewise digital layout generation
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Application No.: US15667381Application Date: 2017-08-02
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Publication No.: US10572620B2Publication Date: 2020-02-25
- Inventor: David L. Toub , Larry B. Edwards , Terry L. Maness , Johan Bastiaens
- Applicant: Oracle International Corporation
- Applicant Address: US CA Redwood Shores
- Assignee: Oracle International Corporation
- Current Assignee: Oracle International Corporation
- Current Assignee Address: US CA Redwood Shores
- Agency: Kowert, Hood, Munyon, Rankin & Goetzel, P.C.
- Agent Erik A. Heter
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method and apparatus for performing custom, piecewise digital layout generation is disclosed. The method comprises selecting, in a schematic of a digital circuit displayed in a digital circuit layout tool, a group of transistors and selecting one of a plurality of rows in a physical layout in which the group of transistors is to be placed. After the group of transistors is selected, the digital circuit layout tool may automatically place transistors of the group of transistors in the one of the plurality of rows of the physical layout. The method further comprises repeating selecting of additional groups of transistors, selecting from the plurality of rows, and automatically placing until all transistors of the digital circuit depicted as in the schematic have been placed for use in generating a physical layout plan for the first digital circuit.
Public/Granted literature
- US20190042687A1 Custom Piecewise Digital Layout Generation Public/Granted day:2019-02-07
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