公开(公告)号：US20190042687A1

公开(公告)日：2019-02-07

申请号：US15667381

申请日：2017-08-02

Applicant: Oracle International Corporation

Inventor： David L. Toub ,  Larry B. Edwards ,  Terry L. Maness ,  Johan Bastiaens

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/505 ,  G06F17/5081 ,  G06F2217/74

Abstract: A method and apparatus for performing custom, piecewise digital layout generation is disclosed. The method comprises selecting, in a schematic of a digital circuit displayed in a digital circuit layout tool, a group of transistors and selecting one of a plurality of rows in a physical layout in which the group of transistors is to be placed. After the group of transistors is selected, the digital circuit layout tool may automatically place transistors of the group of transistors in the one of the plurality of rows of the physical layout. The method further comprises repeating selecting of additional groups of transistors, selecting from the plurality of rows, and automatically placing until all transistors of the digital circuit depicted as in the schematic have been placed for use in generating a physical layout plan for the first digital circuit.

公开(公告)号：US10572620B2

公开(公告)日：2020-02-25

申请号：US15667381

申请日：2017-08-02

Applicant: Oracle International Corporation

Inventor： David L. Toub ,  Larry B. Edwards ,  Terry L. Maness ,  Johan Bastiaens

IPC: G06F17/50

Abstract: A method and apparatus for performing custom, piecewise digital layout generation is disclosed. The method comprises selecting, in a schematic of a digital circuit displayed in a digital circuit layout tool, a group of transistors and selecting one of a plurality of rows in a physical layout in which the group of transistors is to be placed. After the group of transistors is selected, the digital circuit layout tool may automatically place transistors of the group of transistors in the one of the plurality of rows of the physical layout. The method further comprises repeating selecting of additional groups of transistors, selecting from the plurality of rows, and automatically placing until all transistors of the digital circuit depicted as in the schematic have been placed for use in generating a physical layout plan for the first digital circuit.

公开(公告)号：US20190042684A1

公开(公告)日：2019-02-07

申请号：US15667277

申请日：2017-08-02

Applicant: Oracle International Corporation

Inventor： David L. Toub ,  Larry B. Edwards ,  Terry L. Maness

IPC: G06F17/50

Abstract: A method and apparatus for schematic driven analog circuit layout automation is disclosed. The method comprises a user providing input into schematic of an analog circuit presented in a circuit layout tool to group components into component groups. Responsive to the grouping of components, the circuit layout tool may automatically generate interconnections between components in each group, in accordance with the schematic. Based on user input, the groups may be moved to desired locations within a physical layout plan. Thereafter, the circuit layout tool may automatically generate interconnections between each of the groups, in accordance with the schematic. A physical layout plan may then be provided responsive to completing the generation of interconnections between groups.