A timing controller includes an interface unit configured to receive first image signals corresponding to a first region of a display panel, the first region including a second region which has image signals changed as compared to the second frame and a surrounding region which surrounds the second region, and a first region coordinate signal containing information about the first region during the first frame period from a host, an image processor configured to generate image-processed second image signals corresponding to the second region of the display panel by image-processing the first image signals of the interface unit, and a buffer unit configured to receive a second region signal corresponding to the second region and the image-processed second image signals of the image processor, generate image-processed entire image signals based on the image-processed second image signals, and transmit the image-processed entire image signals to a data driver.