A self-time circuitry is coupled to a first power rail to receive a first voltage and a second power rail to receive a second voltage. The self-time circuitry includes a tracking control circuit which generates a first tracking signal at the first voltage and a second tracking signal at the second voltage. In response to a memory access request, a first number of dummy discharge cells (DDCs) in a first DDC group are activated according to the first tracking signal to discharge a dummy bit line (DBL), and a second number of DDCs in a second DDC group are activated according to the second tracking signal to discharge the DBL. The DBL mimics operations of a bit line in a memory cell array and the DDCs in the first DDC group and the second DDC group mimic operations of bit cells in the memory cell array.