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1.发明授权公开(公告)号：US10580479B2
公开(公告)日：2020-03-03
申请号：US16019477
申请日：2018-06-26
IPC分类号： G11C7/02 , G11C11/408 , G11C7/14 , G06F1/3234 , G11C7/06 , G11C7/10
摘要： A self-time circuitry is coupled to a first power rail to receive a first voltage and a second power rail to receive a second voltage. The self-time circuitry includes a tracking control circuit which generates a first tracking signal at the first voltage and a second tracking signal at the second voltage. In response to a memory access request, a first number of dummy discharge cells (DDCs) in a first DDC group are activated according to the first tracking signal to discharge a dummy bit line (DBL), and a second number of DDCs in a second DDC group are activated according to the second tracking signal to discharge the DBL. The DBL mimics operations of a bit line in a memory cell array and the DDCs in the first DDC group and the second DDC group mimic operations of bit cells in the memory cell array.
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2.发明申请公开(公告)号：US20190392889A1
公开(公告)日：2019-12-26
申请号：US16019477
申请日：2018-06-26
IPC分类号： G11C11/408 , G11C7/14 , G11C7/10 , G11C7/06 , G06F1/32
摘要： A self-time circuitry is coupled to a first power rail to receive a first voltage and a second power rail to receive a second voltage. The self-time circuitry includes a tracking control circuit which generates a first tracking signal at the first voltage and a second tracking signal at the second voltage. In response to a memory access request, a first number of dummy discharge cells (DDCs) in a first DDC group are activated according to the first tracking signal to discharge a dummy bit line (DBL), and a second number of DDCs in a second DDC group are activated according to the second tracking signal to discharge the DBL. The DBL mimics operations of a bit line in a memory cell array and the DDCs in the first DDC group and the second DDC group mimic operations of bit cells in the memory cell array.
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公开(公告)号：US10319432B2
公开(公告)日：2019-06-11
申请号：US15801733
申请日：2017-11-02
IPC分类号： G11C11/419 , G11C11/4091 , G11C7/08
摘要： Control circuits for memory devices are described. The control circuits may be configured such that the duration of the pulses delivered to the sense amplifiers increases with increasing parasitic RC delays. That is, the larger the parasitic RC delay along a line connecting a drive circuit to the sense amplifiers, the larger the duration of the pulses delivered. In some embodiments, a feedback line may be inserted between the end of the output signal line and the drive circuit to route the control pulses back to the drive circuit. The drive circuit may be arranged such that the duration of the pulses with which the sense amplifiers are driven depends on the delay experienced along the feedback line. In this way, the longer the RC delay arising along the feedback line, the larger the durations of the pulses.
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公开(公告)号：US20190013064A1
公开(公告)日：2019-01-10
申请号：US15801733
申请日：2017-11-02
IPC分类号： G11C11/419 , G11C7/08 , G11C11/4091
摘要： Control circuits for memory devices are described. The control circuits may be configured such that the duration of the pulses delivered to the sense amplifiers increases with increasing parasitic RC delays. That is, the larger the parasitic RC delay along a line connecting a drive circuit to the sense amplifiers, the larger the duration of the pulses delivered. In some embodiments, a feedback line may be inserted between the end of the output signal line and the drive circuit to route the control pulses back to the drive circuit. The drive circuit may be arranged such that the duration of the pulses with which the sense amplifiers are driven depends on the delay experienced along the feedback line. In this way, the longer the RC delay arising along the feedback line, the larger the durations of the pulses.
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