A data correction filter includes an equalizer circuit, first, second, and third asynchronous comparators, an error amplifier, a multiplexer, a delay circuit, first and second exclusive-OR gates, and first and second integrator circuits. The first asynchronous comparator is coupled to the equalizer circuit. The second and third asynchronous comparators are coupled to the equalizer circuit and the error amplifier. The multiplexer is coupled to the first, second, and third asynchronous comparators. The delay circuit is coupled to the first asynchronous comparator. The first exclusive-OR gate is coupled to the delay circuit and the multiplexer. The second exclusive-OR gate is coupled to the first asynchronous comparator and the multiplexer. The first integrator circuit is coupled to first exclusive-OR gate and the equalizer circuit. The second integrator circuit is coupled to the second exclusive-OR gate and the error amplifier.