Invention Grant
- Patent Title: Method and apparatus for reducing coupling between word lines and control gate lines in a flash memory system
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Application No.: US16118272Application Date: 2018-08-30
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Publication No.: US10586595B2Publication Date: 2020-03-10
- Inventor: Xiaozhou Qian , Kai Man Yue , Guang Yan Luo
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP (US)
- Priority: CN201810626274 20180615
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/26

Abstract:
A method and apparatus are disclosed for reducing the coupling that otherwise can arise between word lines and control gate lines in a flash memory system due to parasitic capacitance and parasitic resistance. The flash memory system comprises an array of flash memory cells organized into rows and columns, where each row is coupled to a word line and a control gate line.
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