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公开(公告)号：US10586595B2
公开(公告)日：2020-03-10
申请号：US16118272
申请日：2018-08-30
Applicant: Silicon Storage Technology, Inc.
Inventor： Xiaozhou Qian , Kai Man Yue , Guang Yan Luo
Abstract: A method and apparatus are disclosed for reducing the coupling that otherwise can arise between word lines and control gate lines in a flash memory system due to parasitic capacitance and parasitic resistance. The flash memory system comprises an array of flash memory cells organized into rows and columns, where each row is coupled to a word line and a control gate line.
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