Invention Grant
- Patent Title: Self-selecting memory array with horizontal bit lines
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Application No.: US15925536Application Date: 2018-03-19
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Publication No.: US10593399B2Publication Date: 2020-03-17
- Inventor: Lorenzo Fratin , Fabio Pellizzer , Agostino Pirovano , Russell L. Meyer
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G11C13/00
- IPC: G11C13/00 ; H01L23/528

Abstract:
Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material (SSM). Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.
Public/Granted literature
- US20190287614A1 SELF-SELECTING MEMORY ARRAY WITH HORIZONTAL ACCESS LINES Public/Granted day:2019-09-19
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