Invention Grant
- Patent Title: Integrated capacitors on lead frame in semiconductor devices
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Application No.: US16398022Application Date: 2019-04-29
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Publication No.: US10593614B2Publication Date: 2020-03-17
- Inventor: Fulvio Vittorio Fontana , Giovanni Graziosi
- Applicant: STMICROELECTRONICS S.R.L.
- Applicant Address: IT Agrate Brianza
- Assignee: STMICROELECTRONICS S.R.L.
- Current Assignee: STMICROELECTRONICS S.R.L.
- Current Assignee Address: IT Agrate Brianza
- Agency: Seed Intellectual Property Law Group LLP
- Priority: IT10201620111 20160226
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L21/48 ; H01L21/56 ; H01L23/31 ; H01L49/02

Abstract:
In an embodiment, a semiconductor device includes: a lead-frame including one or more electrically conductive areas, one or more dielectric layers over the electrically conductive area or areas, one or more electrically conductive layer over the one or more dielectric layers thus forming one or more capacitors each including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer. The semiconductor device also includes a semiconductor die on the lead-frame electrically connected to the one or more electrically conductive layers.
Public/Granted literature
- US20190259691A1 METHOD OF INTEGRATING CAPACITORS IN SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE Public/Granted day:2019-08-22
Information query
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